Available from SynaptiCAD the Timing Diagram Editor Company
VeriLogger Extreme is a completely new, high-performance compiled-code Verilog 2001 simulator that significantly reduces simulation debug time. VeriLogger Extreme offers fast simulation of both RTL and gate-level simulations with SDF timing information. VeriLogger Extreme supports design libraries and design flows for all major ASIC and FPGA vendors, including Actel, Altera, Atmel, LSI Logic, QuickLogic, and Xilinx. VeriLogger Extreme also comes with BugHunter Pro a graphical Verilog/VHDL integrated development environment, which supports debugging with all major HDL simulators. BugHunter supports source-level debugging, a waveform compression engine for high-speed waveform dumping and viewing, and graphical test bench generation features for rapidly testing HDL models.