TestBencher Pro provides designers with a graphical environment for rapidly generating and testing bus-functional models for VHDL and Verilog. Graphical timing diagrams and a top-level template file are used to generate the test bench code. The graphical timing diagrams represent reusable bus transactions like a PCI bus read or write cycle. The top-level template file connects the transactions to the model under test and it defines how the transactions are applied to the model under test.
TestBencher generates all of the low-level transaction code, verification code, sequence detection, error reporting and file I/O code allowing you to focus on the design and operation of the model. It accelerates development for both expert and novice users by supporting random data generation, transaction management, and hierarchical models.
TestBencher also automates the build process by controlling external simulators and compilers through its’ graphical interface. This is particularly useful when multiple tools are needed to compile and simulate a project. TestBencher handles all of the details of creating make files and issuing commands to dynamically link library or byte code.

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